Enhanced I/O Buffer Predriver Modeling under Power/Ground Supply Voltage Variation

Abstract

This paper presents I/O buffer nonlinear behavioral modelling that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variation. Model structure and I/O device characterization along with extraction procedure are described. I/O buffer’s last stage is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The predriver’s mathematical model structure is derived from the analysis of the large signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure is considered in this work. Timing series data, which reflects the observed the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, is used to train the NN model. The proposed model is implemented in time domain solver and validated against reference transistor level (TL) model and the state of the art input-output buffer information specification (IBIS) behavioral model under different scenarios. The jitter analysis is performed using the eye diagram tool through analyzing its different metrics values.